1. Field
Exemplary embodiments of the present invention relate generally to a non-volatile memory device and a method for operating the non-volatile memory device.
2. Description of the Related Art
Non-volatile memory devices retain data stored therein even when power supply is cut off. Non-volatile memory devices store data by taking advantage of a threshold voltage change of memory cells by controlling the amount of charges held in a conductive band of a floating gate.
When a program pulse is applied to a floating gate, the threshold voltage of a memory cell rises. The threshold voltage of a memory cell may be made different according to the value of a data to be stored in the memory cell by using the program pulse. However, since the characteristics of a plurality of memory cells in a non-volatile memory device are different, the threshold voltages of the memory cells storing the same data are not the same but they form a distribution.
Meanwhile, a plurality of memory cells in a non-volatile memory device are coupled to bit lines. Each of the bit lines is coupled to a page buffer. A page buffer may drive its corresponding bit line with a predetermined voltage level to perform a predetermined operation, such as a read operation or a write operation, on the selected memory cells that are coupled to the corresponding bit line, or sense the voltage of the bit line and store and output the sensed value. A page buffer typically includes one or more latches to store a data inputted from an external device and drive the corresponding bit line with a predetermined voltage, or to sense the voltage of the corresponding bit line, store the data corresponding to the voltage of the bit line, and transfer the data to an external device.
Among the one or more latches included in each page buffer, a cache latch stores the data of selected memory cells during a data read operation, and drives a line for transferring the data to the external device based on a stored value. Hereafter, the transferring of the data stored in the cache latch of a page buffer to an external device is described with reference to FIG. 1.
FIG. 1 shows a part of a non-volatile memory device for describing how data of a cache latch are transferred.
Referring to FIG. 1, the non-volatile memory device may include a cache latch 110, a switch 120, a pair of an input/output line IO and an input/output bar line IOB, and a pre-charger 130.
The cache latch 110 may include a data node Q and a data bar node QB. During a read operation, the data of a bit line (not shown in FIG. 1) may be sensed and stored in the cache latch 110. When a column selection signal CS<0> is enabled, the switch 120 is turned on to couple the cache latch 110 and the pair of the input/output line IO and the input/output bar line IOB to each other.
The pre-charger 130 may pre-charge the pair of the input/output line IO and the input/output bar line IOB with a power source voltage VCC before the pair of the input/output line IO and the input/output bar line IOB is coupled to the cache latch 110. When the data node Q and the data bar node QB of the cache latch 110 are coupled to the input/output line IO and the input/output bar line IOB of the pair, a discharge path may be formed by one inverter among the inverters IV1 and IV2 of the cache latch 110 to drop the voltage level of one input/output line between the input/output line IO and the input/output bar line IOB of a pair. When the voltage difference between the input/output line IO and the input/output bar line IOB of the pair is greater than a predetermined level, the data may be detected and outputted.
However, as the integration degree of non-volatile memory devices increases with ever-decreasing power source voltage, the above-described discharge rate becomes slow and eventually, it takes longer time for the voltage difference between an input/output line IO and an input/output bar line IOB of a pair to reach a predetermined level. This becomes an obstacle to the high-speed operation of the non-volatile memory devices.